1. Field of the Invention
The present invention relates generally to scan chains used in processors, and more particularly, to a design that will disable the scan chain during functional mode of the processor for power saving.
2. Description of the Related Art
Scan chains are used for testing and debugging microprocessors and other LSI chips. These scan chains can also be used for bringing up a chip during the initial boot up sequences. Once the testing or the initial boot up sequences are completed, the scan chains are no longer necessary for the functional operation of a processor. Although these scan chains do not have a functional purpose they are not removed from the processor or disconnected. Since these scan chains are kept connected, whenever the data of the functional paths change, the data change will propagate through the scan chains. This propagation results in the consumption of some unnecessary power.
Referring to FIG. 1 in the drawings, reference numeral 100 illustrates a block diagram depicting the conventional implementation of scan chains in a microprocessor. The latch bits 104, 112, 120, 130, 138, and 146 are connected to each other in the lateral direction. In a typical design, there is a scan chain segment 150 that bridges the scan output of one latch bit 138 and the scan input of another latch bit 146. The scan chain segment 150 and other scan chain segments (not labeled) consist of a long wire and two buffers 142 and 144. These scan chain segments exist between all of the latch bits in a processor containing a scan chain. Accordingly, if a scan signal travels from the output of latch bit 138 to the input of latch bit 146, it passes through buffers 142 and 144.
A trace of a scan signal through a scan chain must begin with the Scan In signal 102. This Scan In signal 102 enters the latch bit 104 as an input. Communication channel 106 feeds the output of latch bit 104 into buffer 108. Communication channel 106 denotes the scan output port of latch bit 104. Buffer 108 outputs the scan signal into the next buffer 110. Buffer 110 then distributes the signal as an input to latch bit 112. Communication channel 114 distributes the scan output signal from the output of latch bit 112 to buffer 116. This process will continue to repeat itself until the last latch bit in the scan chain has been scanned. In particular, in FIG. 1, buffer 116 outputs the scan signal into the next buffer 118, which then distributes the signal as an input to latch bit 120. The output of latch bit 120 is conveyed via communication channel 122 to the input of buffer 124, the output of which conveys the signal to the input of buffer 126. The signal is then conveyed from the output of buffer 126 to the input of latch bit 130. The output of latch bit 130 is conveyed via communication channel 132 to the input of buffer 134, the output of which conveys the signal to the input of buffer 136. The signal is then conveyed from the output of buffer 136 to the input of latch bit 138. The output of latch bit 138 is conveyed via communication channel 140 to the input of buffer 142, the output of which conveys the signal to the input of buffer 144. The signal is then conveyed from the output of buffer 144 to the input of latch bit 146. The last latch bit 146 produces the Scan Out signal 148. This is how a scan signal passes through a scan chain involving these latch bits. In functional mode of the processor these latch bits distribute information to each other through logic circuits, 152, 154, 156, and 158. For example, latch bit 104 will send information through logic circuit 152 to distribute a decoded signal to latch bit 120. During functional mode of a microprocessor these scan chains are unnecessary.
Referring to FIG. 2 of the drawings, reference numeral 200 depicts a block diagram of a conventional latch bit. The scan control signal 205 enables latch 1 220 to carry out a scan of the complete latch bit 200. In scan mode, the scan in port 210 is selected by the scan control signal 205 and provides the input to latch 1 bit 220. Latch 1 220 and latch 2 225 combined make up the latch bits that correspond to latch bits 104, 112, 120, 130, 138 and 146 in FIG. 1. The primary in port 215 is also an input to latch 1 220. This primary in port 215 is used during the functional mode of the processor. In the functional mode of the processor, the signal path is from primary in 215 to primary out 230. In the scan mode of the processor, the path is from scan in 210 to both the primary out 230 and the scan out 235. In this conventional latch bit, the primary out port 230 and the scan out port 235 are at the same node 240.
This conventional latch bit causes some problems. The primary out port 230 and the scan out port 235 are at the same node 240. Therefore, the scan out port 235 will toggle during the functional mode of the processor, and the data will propagate through the nets of the scan chain until the scan chain hits a latch bit where the primary in port 215 is selected. During functional mode, every latch bit will be selected for the primary in port 215. As shown in FIG. 1, the latch bits are bridged by a long wire and several buffers illustrated as scan chain segment 150 in FIG. 1. The toggling of these wires and buffers during primary signal distribution leads to unnecessary power consumption. Therefore, there is a need for a method and/or apparatus to modify conventional scan chains to consume less energy during the functional mode of a processor.